1. Field of the Invention
The present invention is related to an encoding method, an encoding apparatus, a decoding method, and also a decoding apparatus, capable of compressing/decompressing data.
2. Description of the Related Art
As an example of known encoding systems, a description will be made of an arithmetic encoding operation capable of achieving a high compression rate. Before describing a concrete operation, a conceptional idea of a binary arithmetic encoding operation is explained with reference to FIG. 16. An arithmetic encoding operation is realized in such a manner that a coordinate system value of a binary decimal number on a numerical straight line defined larger than, or equal to 0.0 and smaller than 1.0 becomes a code C. In a process stage, a range defined on the above-explained numerical straight line is divided as a valid section (effective section) width A in direct proportion to an appearance probability of a binary symbol, and a partial section corresponding to an actually appearing symbol is divided as a new valid section, which is repeatedly carried out. MPS (More Probable Symbol) corresponds to a superior symbol which indicates a data value of higher appearance probability. LPS (Less Probable Symbol) corresponds to an inferior symbol which indicates a data value of lower appearance probability. One coordinate value which is updated by a final symbol within a valid section is outputted as a code. During process operation, the code C is calculated as a lower bound value of a valid section, and this code C is updated as well as a width of a valid section, which is equal to a difference between an upper bound value and a lower bound value in this drawing. As the final code, it is also possible to select a coordinate value where a significant digit number is minimum within a valid section where 0 subsequent to a tail of a coordinate system is cut off.
In general, to practically execute the arithmetic encoding operation, a subtraction type arithmetic encoding operation is employed which is adaptive to cope with an increase in a significant digit number when a code calculation is carried out. It is assumed in the below-mentioned description that an arithmetic code indicates a subtraction type arithmetic code. FIG. 17 is a diagram for representing a conceptional idea of a subtraction type arithmetic encoding operation and a conceptional idea of a renormalizing process operation. A symbol LSZ corresponds to a partial section allocated to LPS, and an approximate value is selected from a previously prepared table based upon appearance probability of the symbols. In this step, when the valid section becomes smaller than xc2xd, such a renormalizing process operation is carried out that the valid section is multiplied by power of 2 so as to be enlarged larger than, or equal to xc2xd. As a consequence, a digit number of a decimal portion is kept constant during a calculation. At this time, in an integer portion, these digits which constitutes xe2x80x981xe2x80x99 subsequent to a decimal point and xe2x80x980xe2x80x99 of an upper digit of this xe2x80x981xe2x80x99, may be changed by a carry-up propagation in a coordinate calculation which will be performed later. Thus, the values are not defined. Since digits upper than these values do not contain the carry-up propagation, these upper digits can be sent out from an encoder.
Both the most typical encoder (Encoder) of the subtraction type arithmetic encoding operation and also the most typical decoder (Decoder) thereof may be realized by employing the table and the process flow, which are described in the International Standard Recommendation T. 82 of ITU-T. Here, this arithmetic encoding operation will the be referred to as a QM coder, and while data to be encoded is used as a binary image, the calculation process operations of both the encoding operation and the decoding operation defined in the above-explained preceding technical publication will now be described. In this case, when the encoding calculation process operation and the decoding calculation process operation of the QM coder are carried out, the correcting techniques for partial sections corresponding to the symbols disclosed in Japanese Patent No. 2128115 (U.S. Pat. Nos. 5,307,062, 5,404,140) are employed. This correcting technique will be explained with reference to FIG. 18, in which numeral values are expressed by the decimal system. In FIG. 18(a), while the valid section is 0.6, 0.2 is selected as LSZ which may occupy ⅓ of the entire section. Since this LSZ is not larger than xc2xd, LSZ is allocated to LPS, and the remaining section is allocated to MPS. However, as shown in FIG. 18(b), when LSZ may occupy ⅔ of the entire section, which exceeds xc2xd thereof, since the symbol correspondences between the appearance probability rate and the actual occupation rate are inversed, the correction is performed by simply exchanging the sections by both MPS and LPS so as to suppress deterioration of the encoding performance. This is referred to as an xe2x80x9cconditional MPS/LPS exchangexe2x80x9d.
FIG. 19 and FIG. 20 respectively represent block structural diagrams of an encoder 1A and a decoder 1B of QM coder, which are provided to explain operations with respect to both the encoding calculation process operation and the decoding calculation process operation. In this prior art, both an image memories 5A and 5B are assumed to be arranged inside the encoder 1A and the decoder 1B, respectively.
In FIG. 19 and FIG. 20, reference numeral 2 shows a context (Context), reference numeral 3 indicates a pixel (Pixel) which should be encoded, reference numeral 4 represents a code, and reference numerals 5A and 5B are image memories. Reference numeral 7 shows a prediction value table MPS, reference numeral 8 indicates a state table ST, reference numeral 9 represents an LPS section width table LSZ, reference numeral 10 shows an MPS state transition destination table NMPS, reference numeral 11 denotes an LPS state transition destination table NLPS, reference numeral 12 shows a prediction value inversion judgement table SWTCH, reference numerals 13A and 13B show arithmetic encoders, reference numeral 14 represents a symbol, and also reference numerals 15A and 15B represent pixel symbol converters.
Operations of the QM coder will now be explained. The image memory 5A employed in the QM encoder 1A stores thereinto an entered image 6, and refers to a predetermined encoded pixel by a model template with respect to the pixel 3 which should be encoded, and outputs the pixel 3 which should be encoded and the context 2 equal to a pattern produced from the pixel at the same time.
On the other hand, the image memory 5B employed in the QM decoder 1B stores therein the decode pixel 3 which has already been decoded, produces the context 2 with respect to such a pixel that should be decoded later from this stored pixel 3, and then outputs the produced context 2. The image memory 5B obtains such a pixel that should be decoded and is decoded by using this context to store thereinto this pixel which should be decoded, and then, outputs an image 6.
In the QM coder, prediction coincident probability of a pixel value is predicted in every context with respect to the pixel which should be encoded/decoded, and the encoding/decoding operations are executed, while the QM coder erans in connection with this variation. Learning is carried out by rewriting two variable tables 7 and 8 in which the context 2 is used as an index. One of these variable tables corresponds to a prediction value table MPS7 of each 1 bit (will be referred to as xe2x80x9cMPS table 7xe2x80x9d hereinafter) which stores thereinto as a prediction value in a state in which a pixel value MPS whose appearance probability is high. The other corresponds to a state table ST8 of each 7-bit (will be referred to as an xe2x80x9cST table 8xe2x80x9d hereinafter) which stores thereinto state numbers (0 to 112). The state numbers are produced by classifying a degree of prediction coincidence probability of a prediction value into 113 pieces of states (State) in total.
Other than the variable tables 7 and 8, there are constant tables (probability prediction table) 9 to 12, while referring to state numbers (State) as an index when the encoding/decoding operations are carried out. In other words, these constant tables are an LPS section width table LSZ9 in which an LPS section width is expressed by 16 bits (will be referred to as an LSZ table 9 hereinafter), an MPS state transition destination table NMP10 in which an MPS transition destination is expressed by 7 bits (will be referred to as an NMPS table 10 hereinafter); an LPS state transition destination table NLPS11 in which an LPS transition destination is-expressed by 7 bits (will be referred to an NLPS table 11 hereinafter), and also a prediction value inversion judgement table SWTCH12 in which a prediction value inversion judgement is expressed by 1 bit (will be referred to as an SWTCH table 12 hereinafter). It is now assumed that the names of the alphabetical variable/constant tables indicated in this explanation are arrangement names employed in process flow operations (will be explained later).
The calculating units employed in the arithmetic encoder 13A/arithmetic decoder 13B refer to the LSZ table 9, and this LSZ table 9 is not directly related to learning of adaptive prediction. Inside the arithmetic encoder 13A/arithmetic decoder 13B, the calculation is carried out by employing the LSZ value, and when the calculation precision is lowered, the renormalizing process operation (Renormalization) is carried out. When this renormalizing process operation is carried out, learning is performed at the same time.
If the encoding/decoding symbol 14 when the renormalizing process operation is executed corresponds to a superior symbol, the NMPS value is written into the ST table 8, whereas if the encoding/decoding symbol 14 when the renormalizing process operation is executed corresponds to the inferior symbol, then the NLPS value is written in the ST table 8, and the state is updated. The superior symbol indicates that the pixels 3 to be encoded/decoded are equal to the prediction value MPS7, whereas the inferior symbol indicates that the pixels 3 to be encoded/decoded are not equal to the prediction value MPS7. When the encoding operation is carried out, the pixel symbol converter 15A outputs the symbol 14 to the arithmetic encoder 13A, whereas when the decoding operation is performed, the decoder 13B outputs the symbol 14 to the symbol pixel converter 15B.
Also, when the renormalizing process operation is caused by the inferior symbol, if the prediction coincidence probability thereof is substantially equal to xc2xd, the MPS value 7 is inversed (calculation 1-MPS) and the inversed MPS value 7 is written into the MPS table 7. It can be judged as to whether or not the coincidence probability is equal to xc2xd by using the SWTCH value 12 as a flag.
As explained above, the updating process operation is carried out with respect to each of the two variable tables ST8 and MPS7, and these variable tables ST8/MPS7 must be separately managed.
In FIG. 21, there is shown an example of a constant table. While the constant table of the actual QM coder is constituted by 113 states, a description will now be made of a simple model. In this example, the constant table is constituted by 10 pieces of states, and it is assumed that the appearance probability of LPS between a state 0 to a state 9, is decreased by steps defined from 0.5 to 0.05. Under state i, when the renormalizing process operation is executed during the MPS process operation, the NMPS value is referred, and also the state number stored under the context is updated to (i+1). If i=9, this state cannot be further transferred to such a state having lower appearance probability than that of the own state 9, and therefore this state remains. Also, when the LPS process operation is carried out under state i, the NLPS value is referred, and the state number stored under the context is updated to (ixe2x88x921). If i=0, this state cannot be further transferred to such a state having higher appearance probability than that of the own state xe2x80x9c0xe2x80x9d, and therefore this state remains. At this time, since SWTCH=1, the prediction value MPS stored under the context is updated to an inversed value (1-MPS). In this case, it is ideal that LSZ is set to a probability value. However, since the valid section width is present between 0.5 and 1.0, LSZ is determined in such a manner that the errors caused by these aspects should be reduced as being permitted as possible. The constant table does not always contain the actual probability. In this drawing, an average value of the probability as to both the state i and the state (i+1) is simply described in this constant table.
FIG. 22 represents a bit arrangement of an encoding register C 30A, a bit arrangement of a decoding register C 30B, and a bit arrangement of a section width register A 31, which are used in both the encoding calculation process operation and the decoding calculation process operation. In the encoding register C 30A, a decimal point is set between a bit 15 and bit 16, a decimal part xe2x80x9cxxe2x80x9d (16 bits) corresponds to a calculating unit Cx32 based upon LSZ9, and when a carry is performed, this decimal part is propagated to an upper integer part. In the integral part, symbol xe2x80x9cbxe2x80x9d (8 bits) corresponds to a byte output unit Cb33, and symbol xe2x80x9ccxe2x80x9d (1 bit) corresponds to a carry-up judging unit Cc34. The carry-up is propagated to a code byte outputted just before the carry-up, and may be propagated up to an output byte before this code byte, if necessary. In the encoding process stage, the C register value is updated in such a manner that this C register value becomes as a code 4 a lower bound value of a section corresponding to the coded symbol.
In the decoding register C 30B, both a lower digit register CLOW 36 and a high digit register CHIGH 37 set a decimal point between a bit 23 and a bit 24; symbol xe2x80x9cbxe2x80x9d (8 bits) corresponds to Cb36 identical to a byte input unit (CLOW register 35); and symbol xe2x80x9cxxe2x80x9d (17 bits) corresponds to a calculating unit Cx (CHIGH register 37) 38 based upon LSZ9. In the decoding process stage, the C register value is updated in such a manner that this C register value becomes an offset value to a code 4 from a lower bound value of a section corresponding to the decoded symbol. This code 4 is a coordinate value within this section.
The input/output operations of the code byte in Cb are carried out when shift numbers of the C registers 30A, 30B, and the A register 31 by the renormalizing process operation are counted by CT50 equal to an auxiliary variable other than a register, and the counted value becomes 0. Both an initial value and a re-setting value of CT50 are equal to 8. As the encoding register defined in the preceding technical publication (recommendation T.82), there is a Cs between Cx and Cb, but is omitted for the sake of a simple explanation. If Cs is provided, a digit number thereof must be added to an initial value of a variable CT. Also, an integer part bit 24 of the encoding register is not defined, but is not required in this prior art. While the CLOW register 36 is defined by 16 bits, since lower-digit 8 bits lower than Cb are not used, the lower-digit 8 bits are omitted. The above-explained changes in the description never give any adverse influence to the encoding performance.
In the section width register A 31 which is commonly used in both the encoding operation and the decoding operation, in correspondence with the decimal points of the encoding/decoding registers 30A/30B, xe2x80x9caxe2x80x9d (16 bits) is arranged as a decimal part in conformity with an xe2x80x9cxxe2x80x9d register unit, and an integer part (bit 16) becomes xe2x80x9c1xe2x80x9d only by the value of an initial state. A section width (or, section size) is updated to either A-LSZ (lower section width) or LSZ (upper section width), and this section width is renormalized in such a manner that a bit 15 indicative of a xc2xd weight becomes xe2x80x9c1xe2x80x9d except for the initial value (integer part=xe2x80x9c1xe2x80x9d). Since the section width is kept larger than, or equal xc2xd, even when any LSZ9 is selected as the upper section width, securing of the lower section is guaranteed. In the renormalizing process operation, the A register 31, and the C register 30A, or 30B are enlarged at the same time.
In the QM coder, normally, the upper section LSZ9 which constitutes the fixed size with respect to the state is allocated to LPS. When the lower section becomes smaller than the upper section, xe2x80x9cconditional MPS/LPS exchangexe2x80x9d in which the upper section LSZ9 is allocated to MPS is carried out. The renormalizing process operation is necessarily carried out when LPS is encoded/decoded, and also MPS is encoded/decoded by applying xe2x80x9cconditional MPS/LPS exchangexe2x80x9d.
First, the encoding calculation process operation will now be explained with reference to a concrete process flow operation.
When the encoding calculation process operation is commenced, an initial value of the C register 30A (see FIG. 22) is 0; an initial value of the A register 31 is 0x10000; and an initial value of an auxiliary variable CT50 becomes 8 based upon the specification of the above-explained C register. Also, both a prediction value MPS[CX]7 with respect to all of contexts (reference patterns) CX2 (FIG. 19), and an initial value of a state ST[CX]8 are assumed as 0. Then, when the coding calculation process operation is ended, a process operation of a definition for sweeping out the content of the encoding register 30A as a final code 4 is performed.
FIG. 23 is an encoding process (ENCODE) flow operation for switching a process operation called from coincidence/incoincidence between the pixel value 3 to be encoded and the prediction value 7. At a step S111, a judgement is made as to whether or not the pixel value PIX3 is made coincident with the prediction value MPS[CX]7. If the pixel value PIX3 is made coincident with the prediction value MPS[CX]7, then MPS is encoded, whereas if the pixel value PIX3 is not made coincident with the prediction value MPS[CX]7, LPS is encoded. At a step S112, while CODELPS (LPS encoding) is called, LPS is encoded. At a step S113, while CODEMPS (MPS encoding) is called, MPS is encoded.
FIG. 24 shows a CODELPS process flow operation called in such a case that the pixel value 3 to be encoded is not made coincident with the prediction value 7, namely, LPS is encoded. First, at a step S120, LSZ is assumed as LSZ [ST[CX]]. At a step S121, the value of the A register 31 is temporarily updated to the lower section width. When such a judgement is made at a step S122 that the LSZ value (upper section width) is larger than the A value (lower section width) (namely, the answer is xe2x80x9cYESxe2x80x9d), the xe2x80x9cconditional MPS/LPS exchangexe2x80x9d is applied, and while both the value of the A register 31 and the value of the C register 30A remain, the valid section is updated to a smaller lower section. When, the LSZ (upper section width) is smaller than, or equal to the A value (lower section width) (namely the answer is xe2x80x9cNOxe2x80x9d), the lower section width (present A register 31) is added to the C register 30A at a step S123, and thereafter, while the A register 31 is set as LSZ, the valid section is updated to a smaller upper section at a step S124. If it is judged at a step S125 that the constant SWTCH value 12 is equal to 1, then the prediction value 7 (MPS table) is inversed/updated at a step S126. While LPS is encoded, a state transition is performed with reference to the NLPS table 11 at a step S127, and RENORME is called to execute the renormalizing process operation at a step S128.
FIG. 25 represents a CODEMPS process flow operation called in such a case that the pixel value 3 to be encoded is made coincident with the prediction value 7, namely called when MPS is coded. First, at a step S130, LSZ is assumed as LSZ [ST [CX]]. At a step S131, the value of the A register 31 is temporarily updated to the lower section width. If it is judged at a step S132 that the value of the A register 31 is larger than, or equal to 0x8000 (namely, the answer is xe2x80x9cNOxe2x80x9d), then this CODEMPS process flow operation is ended. To the contrary, when the value of the A register 31 is smaller than 0x8000 (namely, the answer is xe2x80x9cYESxe2x80x9d), if it is so judged at a step S133 that the LSZ value (upper section width) is smaller than the A value (lower section width) (namely the answer is xe2x80x9cYESxe2x80x9d), then the xe2x80x9cconditional MPS/LPS exchangexe2x80x9d is applied. The lower section width (present A register 31) is added to the C register 30A at a step S134, and thereafter, while the A register 31 is set as LSZ, the valid section is updated to a larger upper section at a step S135. On the other hand, when it is judged at the step S133 that LSZ (upper section width) is larger than, or equal to the A value (low section width) (namely, the answer is xe2x80x9cNOxe2x80x9d), while both the value of the A register 31 and the value of the C register 30A remain, the valid section is updated to a larger lower section. While MPS is encoded, a state transition is performed with reference to the NMPS table 10 at a step S136, and RENORME is called to execute the renormalizing process operation at a step S137.
FIG. 26 indicates a RENORME process flow operation for performing the renormalizing process operation. At a step S141, the value of the A register 31 is shifted to a 1-bit upper digit, and at a step S142, the value of the C register 30A is shifted to a 1-bit upper digit, so that such a calculation is carried out that is equivalent to a multiplication by 2. At a step S143, 1 is subtracted from the variable CT50, and a judgment is made as to whether or not the variable CT50 is equal to 0 at a step S144. When the judgment result is xe2x80x9cYESxe2x80x9d, the 1-byte code 4 is outputted from the C register 30A (Cb), and 8 is again set to the variable CT50 at a step S145. At a step S146, a judgment is made as to whether or not the renormalizing process operation is ended. If the value of the A register 31 is smaller than 0x8000, then the process operations defined from the step S141 to the step S145 are repeatedly carried out. If the value of the A register 31 is larger than, or equal to 0x8000, then the section becomes larger than, or equal to xc2xd, and the process operation is ended.
When the 1-byte code 4 is outputted from the Cb register 33 at the step S145, the carry is judged by the Cc register 34, and the carry is propagated to the code byte which has already been outputted. Then, after the carry is propagated and the code byte is outputted, both the values of the Cb register 33 and the Cc register 34 are cleared.
Next, the decoding calculation process operation will now be described with reference to a concrete process flow operation.
When the decoding calculation process operation is commenced, the C register 30B inputs thereinto a 3-byte code from a decimal part bit 0 to bit 23 as an initial value, and an initial value of the A register 31 is equal to 0x10000. Also, while an initial value of the auxiliary variable CT50 is assumed as 8, both an initial value of the prediction value MPS [CX]7 and an initial value of the state ST[CX]8 with respect to all of the contexts (reference patterns) CX2 are assumed as 0.
FIG. 27 indicates a decoding process (DECODE) operation flow for decoding a pixel which should be decoded. First, at a step S220, LSZ is set to LSZ [ST [CX]]. At a step S221, the value of the A register 31 is temporarily updated to the lower section width. When it is so judged at a step S222 that the value of the code CHIGH register 37 is smaller than the value of the A register 31 (namely, the answer is xe2x80x9cYESxe2x80x9d), the lower section is decoded. Next, when it is so judged at a step S223 that the value of the A register 31 is smaller than 0x8000 (namely, the answer is the answer is xe2x80x9cYESxe2x80x9d), xe2x80x9cMPS_EXCHANGExe2x80x9d is called at a step S224, and RENORMD is called at a step S225, so that the renormalizing process operation is carried out. On the other hand, when it is so judged at the step S223 that the value of the A register 31 is larger than, or equal to 0x8000 (namely, the answer is xe2x80x9cNOxe2x80x9d), MPS is decoded without executing the renormalizing process operation. At a step S226, the pixel value 3 is set to the prediction value 7, so that while both the value of the A register 31 and the value of the C register 30B remain, the valid section is updated to a larger lower section. Also, when it is so judged at the step S222 that the value of the code CHIGH register 37 is larger than, or equal to the value of the A register 31 (namely the answer is xe2x80x9cNOxe2x80x9d), the upper section is decoded. At a step S227, xe2x80x9cLPS_EXCHANGExe2x80x9d is called, and also RENORMD is called at a step S228, so that the renormalizing process operation is carried out. In such a process path for calling both xe2x80x9cMPS_EXCHANGExe2x80x9d and xe2x80x9cLPS_EXCHANGExe2x80x9d, even when the sections to be decoded are determined respectively, if the sections are not compared with each other, then it is not possible to judge as to whether the section to be decoded corresponds to MPS, or LPS. In the called process flow, the pixel value 3 to be decoded is determined.
FIG. 28 shows an LPS_EXCHANGE process flow operation for decoding an upper section. When it is so judged at a step S231 that an LSZ value (upper section width) is smaller than and A value (lower section width) (namely, the answer is xe2x80x9cYESxe2x80x9d), the conditional MPS/LPS exchange is applied. At a step S232, a lower section width (present A register 31) is subtracted from the CHIGH register 37, and thereafter, the A register 31 is set to LSZ at a step S233. At this time, since the upper section is larger than the lower section, MPS is decoded. At a step S234, the pixel value 3 is set as the prediction value 7. At a step S235, a state transition is carried out by referring to the NMPS table 10. When LSZ (upper section width) is larger than, or equal to the A value (lower section width) (namely, the answer is xe2x80x9cNOxe2x80x9d), a lower section width (present A register 31) is subtracted from the CHIGH register 37 at a step S236, and thereafter, the A register 31 is set to LSZ at a step S237. At this time, since the upper section is smaller than the lower section, LPS is decoded. At a step S238, the pixel value 3 is set as a non-prediction value (1-prediction value 7). When it is so judged at a step S239 that the constant SWTCH value 12 is equal to 1, the prediction value (MPS table) 7 is inversed/updated at a step S240. At a step S241, a state transition is carried out with reference to the NLPS table 11.
FIG. 29 shows an MPS_EXCHANGE process flow operation for decoding a lower section. When it is so judged at a step S251 that an LSZ value (upper section width) is smaller than an A value (lower section width) (namely, the answer is xe2x80x9cYESxe2x80x9d), the conditional MPS/LPS exchange is applied, and LPS is decoded. At a step S252, since the pixel value 3 is set to the non-prediction value (1-prediction value 7), while both the value of the A register 31 and the value of the C register 30B remain, the valid section is updated to a smaller lower section. Next, when it is so judged at a step S253 that the constant SWTCH value 12 is equal to 1, the prediction value (MPS table) 7 is inversed/updated at a step S254. At a step S255, a state transition is carried out with reference to the NLPS table 11. On the other hand, when it is judged at a step S251 that LSZ (upper section width) is larger than, or equal to the A value (lower section width) (namely, the answer is xe2x80x9cNOxe2x80x9d), MPS is decoded. At a step S256, the pixel value 3 is set to the prediction value 7. At a step S257, a state transition is carried out with reference to the NMPS table 10.
FIG. 30 indicates a RENORMD process operation for executing the renormalizing process operation. At a step S261, a check is made as to whether or not the variable CT50 is equal to 0. If the judgment result is xe2x80x9cYESxe2x80x9d, then at a step s262 a 1-byte code 4 is inputted to the C register 30B (Cb), and 8 is again set to the variable CT50. At a step S263, the value of the A register 31 is shifted to a 1-bit upper digit, and at a step S264, the value of the C register 30B is shifted to a 1-bit upper digit, so that such a calculation is carried out which is equivalent to a multiplication by 2. At a step S265, 1 is subtracted from the variable CT50. At a step S266, a judgment is made as to whether or not the renormalizing process operation is ended. If the value of the A register 31 is smaller than 0x8000, then the process operations defined from the step S261 to the step S265 are repeatedly carried out. A judgment is made as to whether or not the variable CT50 is equal to 0 at a step S267. When the judgment result is xe2x80x9cYESxe2x80x9d, the 1-byte code 4 is inputted to the C register 30B (Cb), and 8 is again set to the variable CT50 at a step S268.
It should be understood that in the above-described encoding calculation process operation and decoding calculation process operation, in accordance with the preceding technical publication (recommendation T.82) cited as the prior art, the above-mentioned steps S120, S130, and S220 are not described, but are directly described in the respective calculation formulae in the reference format of the LSZ table 9. In this case, for the sake of the below-mentioned descriptions according to the present invention, it is clearly indicated that an index ST [CX] may be consulted as a variable LSZ which is not indicated (namely, not table reference format) in a process flow operation.
In the known encoding method, encoding apparatus, decoding method, and also decoding apparatus, in such a case that the valid section is divided in the arithmetic encoding step and also the arithmetic decoding step, the fixed approximate value is allocated to the partial section irrespective of the valid section width. As a result, since the error contained in the occupation rate and the error contained in the predicted appearance probability of the symbol are increased, there is such a problem that the encoding efficiency is lowered.
The present invention has been made to solve this problem of the prior art, and has an object to provide a data encoding method, a data encoding apparatus, a data encoding method, and a data encoding apparatus, capable of improving an encoding efficiency by employing such a way that in a symbol of a probability for power of xc2xd, while a correction is made in such a manner that an occupation rate of a valid section becomes a probability value, partial sections are allocated.
With the above objects in view, the encoding apparatus of the present invention for predicting appearance probability of an information source symbol, while learning, and for dividing a valid section on a numerical straight line into both a first partial section to which an approximate value of the prediction appearance probability is applied and a second partial section remained in the valid section, to which such an arithmetic code is applied, the arithmetic code setting a partial section corresponding to an appearing symbol as a new valid section, comprises storage means for storing thereinto such a fact that the prediction appearance probability is a specific value, judgement means for judging that the prediction appearance probability is equal to the specific value by referring to the specific value of the storage means, and correction means for correcting an allocation between the first partial section and the second partial section when the judgement means judges that the prediction appearance probability is equal to the specific value.
Also, one of the specific values stored in the storage means may be selected to be xc2xd, and a series of calculation process operations executed in combination with updating of a predicable symbol value of the prediction appearance probability with respect to the relevant symbol may be independently constituted from a calculation process operation of an irrespective symbol.
In encoding operation applied to the relevant symbol, the correction means corrects the allocation, while assuming that both the first partial section and the second partial section are made equal to the valid section. The correction means is comprised of renormalizing means by which only a code is enlarged by executing either a 1-digit shifting process operation or a multiplication by 2 without changing the valid section, and thereafter, representation precision of the valid section is kept maximum by a procedure for calculating a code value, and code outputting means for outputting such a code which can be outputted after the code has been updated by the renormalizing means.